PD Lec 39 - CMOS Latch Up | VLSI | Physical Design
PD Lec 38 - Global Route Congestion | VLSI | Physical Design
PD Lec 35 - Scan Chain Optimization | VLSI | Physical Design
PD Lec 49 - Introduction to CTS | Clock Tree Synthesis | VLSI | Physical Design
PD Lec 50 Clock Tree Synthesis | CTS | VLSI | Physical Design
PD Lec 34 - place-opt understanding | VLSI | Physical Design
PD Lec 24 - Power planning and power mesh creation| Floor-planning | VLSI | Physical Design
PD Lec 40 - Well Tap Cell | VLSI | Physical Design
PD Lec 29 - Cell Orientation and Flipping | Placement | VLSI | Physical Design
PD Lec 41 - Tie Cell | tie low| tie high | VLSI | Physical Design
PD Lec 2 - CMOS Basics part 1 | Tutorial | VLSI | Physical Design
PD Lec 36 - Cell Density of std cells | VLSI | Physical Design
PD Lec 25 - Physical Only Cells | Floor-planning | VLSI | Physical Design
PD Lec 42 - SVT LVT HVT Cell variants | VLSI | Physical Design
PD Lec 51 How to balance skew and latency? | CTS | Clock Tree Synthesis | VLSI | Physical Design
PD Lec 44 - Timing Fixes in placement | Part-2 | VLSI | Physical Design
PD Lec 33 - Placement and Optimization | VLSI | Physical Design
lec 39
PD Lec 46 - Useful Skew | Timing Fixes in placement | VLSI | Physical Design
Mod-04 Lec-39 Point Estimation